Init
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commit
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obj_dir/
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*.vcd
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module overture(
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in,
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out
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);
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input [7:0] in;
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output reg [7:0] out;
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always@(*) begin
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foreach (input[i]) begin
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out[i] = !in[i]
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end
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end
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endmodule
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module overture_tb;
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reg [7:0] in;
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reg [7:0] out;
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overture dut(in, out);
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initial begin
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$dumpfile("overture_dump.vcd");
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$dumpvars();
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in = 8'b00000001;
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out = 8'b00000000;
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#10;
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#10;
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in = 8'b11111111;
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#10;
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in = 8'b00000001;
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#10;
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$finish;
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end
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endmodule
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#!/bin/sh
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# Compile simulation and dump with timing for waveform analysis
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verilator --binary overture.sv overture_tb.sv --top overture_tb --trace-vcd --timing
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# Run compiled simulation
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./obj_dir/Voverture_tb
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# Close old session
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pkill gtkwave
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# Launch new session
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gtkwave overture_dump.vcd &
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