209 lines
5.2 KiB
Org Mode
209 lines
5.2 KiB
Org Mode
* Overture CPU Emulator
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This project implements an emulator for the Overture Instruction set architecture.
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This theoretical ISA is described and implemented in the steam game Turing Complete.
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** ISA Spec
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Overture has 1 byte-wide instructions.
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This contains 6 registers, of which the first 4 have designated uses.
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Additionally, it contains a single input and a single output, which together are mapped as if they were a 7th register.
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The instructions can be split into 4 categories, which can be distinguished by the most significant two bits.
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🔴🔴🟤🟤🟤🟤🟤🟤 Immidiate instructions.
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🔴🟢🟤🟤🟤🟤🟤🟤 Calculate instructions.
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🟢🔴🟤🟤🟤🟤🟤🟤 Copy instructions.
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🟢🟢🟤🟤🟤🟤🟤🟤 Condition instructions.
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* Immediate 🔴🔴🟤🟤🟤🟤🟤🟤
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These instructions represent a number between 0 and 63 (inclusive), which will be put into register 0
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** Assembly Mnemonics
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Generally, these instructions are represented directly by using the value (a number between 0 and 63) directly, since they represent the actual number.
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* Calculate 🔴🟢🟤🟤🟤🟤🟤🟤
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This set of instructions use the 3 least significant bits to indicate which instruction to preform on the contents of Register 1 and Register 2
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🔴🟢🟤🟤🟤🔴🔴🔴 OR
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🔴🟢🟤🟤🟤🔴🔴🟢 NAND
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🔴🟢🟤🟤🟤🔴🟢🔴 NOR
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🔴🟢🟤🟤🟤🔴🟢🟢 AND
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🔴🟢🟤🟤🟤🟢🔴🔴 ADD
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🔴🟢🟤🟤🟤🟢🔴🟢 SUB
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OR 🔴🟢🟤🟤🟤🔴🔴🔴
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A bitwise OR of the values stored in Register 1 and register 2, with the result being placed in Register 3
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NAND 🔴🟢🟤🟤🟤🔴🔴🟢
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A bitwise NAND of the values stored in Register 1 and register 2, with the result being placed in Register 3
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NOR 🔴🟢🟤🟤🟤🔴🟢🔴
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A bitwise NOR of the values stored in Register 1 and register 2, with the result being placed in Register 3
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AND 🔴🟢🟤🟤🟤🔴🟢🟢
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A bitwise AND of the values stored in Register 1 and register 2, with the result being placed in Register 3
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ADD 🔴🟢🟤🟤🟤🟢🔴🔴
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Mathematically adds the the values stored in Register 1 and register 2 together, (without support for a carry), with the result being placed in Register 3
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SUB 🔴🟢🟤🟤🟤🟢🔴🟢
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Subtracts the the values stored in Register 2 from the value stored in register 1 using 2-complements logic, with the result being placed in Register 3
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** Assembly Mnemonics
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The assembly mnemonics for these commands are simply these commands written on their own.
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or
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nand
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nor
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and
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add
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sub
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#+BEGIN_SRC
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const or 64
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const nand 65
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const nor 66
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const and 67
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const add 68
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const sub 69
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#+END_SRC
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* Copy 🟢🔴🟤🟤🟤🟤🟤🟤
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These instructions allow you to represent a copy action between a source location and a destination location.
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There are 7 possible sources to read from:
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🟢🔴🔴🔴🔴🟤🟤🟤 Register 0
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🟢🔴🔴🔴🟢🟤🟤🟤 Register 1
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🟢🔴🔴🟢🔴🟤🟤🟤 Register 2
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🟢🔴🔴🟢🟢🟤🟤🟤 Register 3
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🟢🔴🟢🔴🔴🟤🟤🟤 Register 4
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🟢🔴🟢🔴🟢🟤🟤🟤 Register 5
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🟢🔴🟢🟢🔴🟤🟤🟤 Input
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There are 7 possible destinations to write to:
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🟢🔴🟤🟤🟤🔴🔴🔴 Register 0
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🟢🔴🟤🟤🟤🔴🔴🟢 Register 1
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🟢🔴🟤🟤🟤🔴🟢🔴 Register 2
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🟢🔴🟤🟤🟤🔴🟢🟢 Register 3
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🟢🔴🟤🟤🟤🟢🔴🔴 Register 4
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🟢🔴🟤🟤🟤🟢🔴🟢 Register 5
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🟢🔴🟤🟤🟤🟢🟢🔴 Output
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** Assembly Mnemonics
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A common method of representing the commands is by idividually specifying the parts of the command and adding them together using the OR operator.
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#+BEGIN_SRC
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const cp 128
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const s0 0
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const s1 8
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const s2 16
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const s3 24
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const s4 32
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const s5 40
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const in 48
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const d0 0
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const d1 1
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const d2 2
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const d3 3
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const d4 4
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const d5 5
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const out 6
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#+END_SRC
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Example, which allows you to copy from Register 3 to Register 0
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cp|s3|d0
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** Off Label Usage
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This section is non-normative
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Most common implementations are implemented in such way that if you specify the non-defined option as a source, a zero is read
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🟢🔴🟢🟢🟢🟤🟤🟤 Clear Destination Register
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* Condition 🟢🟢🟤🟤🟤🟤🟤🟤
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This set of instructions allow you to jump to a certain point in your program.
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The destination of the jump is specified by the Register 0.
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The jump will only be performed if the value in Register 3 matches the condition set by the least significant 3 bits of the instruction.
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🟢🟢🟤🟤🟤🔴🔴🔴 Never
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🟢🟢🟤🟤🟤🔴🔴🟢 Equals 0
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🟢🟢🟤🟤🟤🔴🟢🔴 Less Than 0
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🟢🟢🟤🟤🟤🔴🟢🟢 Less than or equals 0
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🟢🟢🟤🟤🟤🟢🔴🔴 Always
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🟢🟢🟤🟤🟤🟢🔴🟢 Not equals 0
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🟢🟢🟤🟤🟤🟢🟢🔴 Greater than or equals 0
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🟢🟢🟤🟤🟤🟢🟢🟢 Greater than 0
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** Assembly Mnemonics
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#+BEGIN_SRC
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const never 192
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const eq 193
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const less 194
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const less_eq 195
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const always 196
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const not_eq 197
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const greater_eq 198
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const greater 199
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#+END_SRC
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