Overture-Verilog/overture_tb.sv

module overture_tb;
	reg [7:0] in;
	reg [7:0] out;
	overture dut(in, out);

	initial begin
		$dumpfile("overture_dump.vcd");
		$dumpvars();
		in = 8'b00000001;
		out = 8'b00000000;

		#10;

		#10;
		in = 8'b11111111;
		#10;
		in = 8'b00000001;
		#10;

		$finish;
	end
endmodule