• Overture CPU Emulator
  • ISA Spec
• Immediate 🔴🔴🟤🟤🟤🟤🟤🟤
  • Assembly Mnemonics
• Calculate 🔴🟢🟤🟤🟤🟤🟤🟤
  • Assembly Mnemonics
• Copy 🟢🔴🟤🟤🟤🟤🟤🟤
  • Assembly Mnemonics
  • Off Label Usage
• Condition 🟢🟢🟤🟤🟤🟤🟤🟤
  • Assembly Mnemonics

Overture CPU Emulator

This project implements an emulator for the Overture Instruction set architecture.

This theoretical ISA is described and implemented in the steam game Turing Complete.

ISA Spec

Overture has 1 byte-wide instructions.

This contains 6 registers, of which the first 4 have designated uses.

Additionally, it contains a single input and a single output, which together are mapped as if they were a 7th register.

The instructions can be split into 4 categories, which can be distinguished by the most significant two bits.

🔴🔴🟤🟤🟤🟤🟤🟤 Immidiate instructions.

🔴🟢🟤🟤🟤🟤🟤🟤 Calculate instructions.

🟢🔴🟤🟤🟤🟤🟤🟤 Copy instructions.

🟢🟢🟤🟤🟤🟤🟤🟤 Condition instructions.

Immediate 🔴🔴🟤🟤🟤🟤🟤🟤

These instructions represent a number between 0 and 63 (inclusive), which will be put into register 0

Assembly Mnemonics

Generally, these instructions are represented directly by using the value (a number between 0 and 63) directly, since they represent the actual number.

Calculate 🔴🟢🟤🟤🟤🟤🟤🟤

This set of instructions use the 3 least significant bits to indicate which instruction to preform on the contents of Register 1 and Register 2

🔴🟢🟤🟤🟤🔴🔴🔴 OR

🔴🟢🟤🟤🟤🔴🔴🟢 NAND

🔴🟢🟤🟤🟤🔴🟢🔴 NOR

🔴🟢🟤🟤🟤🔴🟢🟢 AND

🔴🟢🟤🟤🟤🟢🔴🔴 ADD

🔴🟢🟤🟤🟤🟢🔴🟢 SUB

OR 🔴🟢🟤🟤🟤🔴🔴🔴

A bitwise OR of the values stored in Register 1 and register 2, with the result being placed in Register 3

NAND 🔴🟢🟤🟤🟤🔴🔴🟢

A bitwise NAND of the values stored in Register 1 and register 2, with the result being placed in Register 3

NOR 🔴🟢🟤🟤🟤🔴🟢🔴

A bitwise NOR of the values stored in Register 1 and register 2, with the result being placed in Register 3

AND 🔴🟢🟤🟤🟤🔴🟢🟢

A bitwise AND of the values stored in Register 1 and register 2, with the result being placed in Register 3

ADD 🔴🟢🟤🟤🟤🟢🔴🔴

Mathematically adds the the values stored in Register 1 and register 2 together, (without support for a carry), with the result being placed in Register 3

SUB 🔴🟢🟤🟤🟤🟢🔴🟢

Subtracts the the values stored in Register 2 from the value stored in register 1 using 2-complements logic, with the result being placed in Register 3

Assembly Mnemonics

The assembly mnemonics for these commands are simply these commands written on their own.

or

nand

nor

and

add

sub

const or 64
const nand 65
const nor 66
const and 67
const add 68
const sub 69

Copy 🟢🔴🟤🟤🟤🟤🟤🟤

These instructions allow you to represent a copy action between a source location and a destination location.

There are 7 possible sources to read from:

🟢🔴🔴🔴🔴🟤🟤🟤 Register 0

🟢🔴🔴🔴🟢🟤🟤🟤 Register 1

🟢🔴🔴🟢🔴🟤🟤🟤 Register 2

🟢🔴🔴🟢🟢🟤🟤🟤 Register 3

🟢🔴🟢🔴🔴🟤🟤🟤 Register 4

🟢🔴🟢🔴🟢🟤🟤🟤 Register 5

🟢🔴🟢🟢🔴🟤🟤🟤 Input

There are 7 possible destinations to write to:

🟢🔴🟤🟤🟤🔴🔴🔴 Register 0

🟢🔴🟤🟤🟤🔴🔴🟢 Register 1

🟢🔴🟤🟤🟤🔴🟢🔴 Register 2

🟢🔴🟤🟤🟤🔴🟢🟢 Register 3

🟢🔴🟤🟤🟤🟢🔴🔴 Register 4

🟢🔴🟤🟤🟤🟢🔴🟢 Register 5

🟢🔴🟤🟤🟤🟢🟢🔴 Output

Assembly Mnemonics

A common method of representing the commands is by idividually specifying the parts of the command and adding them together using the OR operator.

const cp 128
const s0 0
const s1 8
const s2 16
const s3 24
const s4 32
const s5 40
const in 48
const d0 0
const d1 1
const d2 2
const d3 3
const d4 4
const d5 5
const out 6

Example, which allows you to copy from Register 3 to Register 0 cp|s3|d0

Off Label Usage

This section is non-normative

Most common implementations are implemented in such way that if you specify the non-defined option as a source, a zero is read

🟢🔴🟢🟢🟢🟤🟤🟤 Clear Destination Register

Condition 🟢🟢🟤🟤🟤🟤🟤🟤

This set of instructions allow you to jump to a certain point in your program.

The destination of the jump is specified by the Register 0.

The jump will only be performed if the value in Register 3 matches the condition set by the least significant 3 bits of the instruction.

🟢🟢🟤🟤🟤🔴🔴🔴 Never

🟢🟢🟤🟤🟤🔴🔴🟢 Equals 0

🟢🟢🟤🟤🟤🔴🟢🔴 Less Than 0

🟢🟢🟤🟤🟤🔴🟢🟢 Less than or equals 0

🟢🟢🟤🟤🟤🟢🔴🔴 Always

🟢🟢🟤🟤🟤🟢🔴🟢 Not equals 0

🟢🟢🟤🟤🟤🟢🟢🔴 Greater than or equals 0

🟢🟢🟤🟤🟤🟢🟢🟢 Greater than 0

Assembly Mnemonics

const never 192
const eq 193
const less 194
const less_eq 195
const always 196
const not_eq 197
const greater_eq 198
const greater 199